EE2700

Fundamentals of Digital System Design (Labs)

Introduction to Digital Circuit Encoding, Simulation, Synthesis and Testing.

Encoding will use Schematics and Hardware Description Language (HDL of VHDL or Verilog style).
Simulation will use ModelSim.
Synthesis will use Field Programmable Gate Arrays (FPGA) on a BASYS2 or BASYS3 Board.
Synthesis may use discrete component Transis-Transistor-Logic (TTL) implementations of logic gates or functions on a Protoboard.
Testing is when student verifies and documents correct functionality, then demonstrates to instructor.

Images and links to assist in learning EE2700 Key Concepts.

Encoding	Simulation	Synthesis	Testing
Schematic  Xilinx VHDL or Verilog	ModelSim Expected Results	TTL  Protoboard FPGA  BASYS2	TTL  Testing FPGA  Testing

Project Progression Images

• Intro
  Inverter
• Intro
  Xilinx
• Mux
   
• Reg
  F-F
• De-
  Bouncer
• De-
  Coder
• En-
  Coder
• En,DB,
  Reg,Dec
• Add,
  ALU
• ALU
  Control
• FSM
   
• CPU
   
• React
  Timer
• Final
  Project
• Sample
  Projects
• References
   
• VGA
  Options
• Vivado
  Sequence

Analysis of an Inverter
Repeat above tests with BASYS2 or BASYS3 Board

Introduction to Digital (HDL) and Schematics
CPU2 VGA ccw .bit   CPU2 Register and Bus Values
Reference (VHDL)   Reference (Verilog)
Project source files (Intro)
Simulation Screenshots Tutorial   Simulation Screenshots Files
Basys2 Board Hardware   Basys2 Reference Manual   Basys2 User Constraint File (UCF)
Basys3 Board Hardware   Basys3 Reference Manual   Basys3 Xilinx Design Constraint File (XDC)
ISE Programming Sequence Tutorial 1   ISE Programming Sequence Tutorial 2
Vivado Programming Sequence Summary   Search this file for Verilog Decoder Tutorial   Vivado Video Tutorials from Xilinx

Multiplexer (MUX) Prelab
Multiplexer TTL Instructions
Multiplexer FPGA Instructions (VHDL)   Multiplexer FPGA Instructions (Verilog)

Flip-Flop (REG) Prelab
Flip-Flops and Registers FPGA Instructions (VHDL)   Flip-Flops and Registers FPGA Instructions (Verilog)
Flip-Flops and Registers TTL Instructions (4x1-bit)   Registers TTL Hardware (2x4-bit)

Debouncer (DB) Prelab
Debouncer FPGA Example
Debouncer FPGA Instructions (VHDL)   Given DB (VHDL)
Debouncer FPGA Instructions (Verilog)   Given DB (Verilog)
Signal Debouncer TTL Instructions   Debouncer TTL Hardware

Decoder Prelab
Decoder Display Block Diagram
Decoder with Display TTL Instructions (demo only)   Decoder with Display TTL Hardware
Decoder FPGA Instructions   Given Decoder (VHDL)   Given Decoder (Verilog)
Basys2 User Constraint File (UCF)
Basys2 Decoder Testing

Encoder Prelab
Encoder Decoder Block Diagram 1
Add Encoder to Decoder FPGA Instructions
Given Encoder Decoder (VHDL)   Given Encoder Decoder VGA (VHDL)
Given Encoder Decoder (Verilog)   Given Encoder Decoder VGA (Verilog)
Encoder Decoder VGA source files   fun VGA source files   1 Block Ram VGA source files
BASYS2 Attached Keypad   BASYS3 Attached Keypad   Encoder Decoder VGA Display
PmodKYPD Resource Center (Encoder)   PmodKYPD Encoder source files

Encoder, Debouncer, Registers and Decoder Prelab and FPGA Instructions
Encoder Reg Decoder Block Diagram 2
En Db Reg (optional Adder) Dec Block Diagram 3 (for students to complete)
decode_4to4.pdf
Given 4-digit Display (VHDL)   Given 4-digit Display (Verilog)
How to combine modules

Arithmetic Logic Unit (ALU) Prelab
ALU FPGA Instructions
Simulation Screenshots Tutorial
Full Adder 2 versions   ALU 1-Bit Wiring and Operations   ALU 4-Bit Wiring   ALU 4-bit Wiring (Optional)
En Db Reg ALU Dec (optional vga) Block Diagram (for students to complete)   ALU Block Diagram (old)
Given VGA (VHDL)   Given VGA (Verilog)
Example of Blocking (=) vs Non-Blocking (<=) Assignment   FPGA demo_en2reg2de_block_non_block.bit

Reaction Timer Prelab and Instructions (HDL version 1)
Reaction Timer Instructions (VHDL version 2)
Reaction Timer Instructions (Verilog version 2)

Finite State Machine (FSM) Prelab and FPGA Instructions
State Diagram
Given FSM 1-process (VHDL unfinished)   Given FSM 3-process (VHDL unfinished)
Given FSM 1-always (Verilog unfinished)   Given FSM 3-always (Verilog unfinished)

Central Processing Unit (CPU) FPGA design instructions and resources (3 Options)

 Option 1, CPU1 (keypad, fixed sequence, no vga)
 Option 2, CPU2 (add vga to Option 1)
   CPU1 and CPU2 Instructions   CPU1 and CPU2 Block Diagram
   CPU1 and CPU2 VHDL files   CPU1 and CPU2 Ver files
   CPU2 ccw Display   CPU2 Display
 Option 3 (programmable sequence, yes vga, two styles available: Utah or Weber)
   CPU3 Instructions
   Utah CPU3 Block Diagram     Utah CPU3 VHDL files     Utah CPU3 Display
   Weber CPU3 Block Diagram   Weber CPU3 VHDL files   Weber CPU3 Display
   CPU3 Suggested Architecture David E. Van Den Bout Lab Book link
 Other Simplified CPU Architectures to consider
   BYU Idaho CPU BYUI CPU link
   UofU CPU UofU CPU link
   Weber CPU part 1 Weber CPU part 2 WEBER CPU link

ALU Control FPGA Instructions (no Prelab)
Suggested Control Plan (3 instructions)
Suggested Control Plan (8 instructions)
Suggested Utah Control Project with VGA (3 instructions); source files
Suggested Weber Control Project with VGA (3 instructions); source files

Prepare Final Project, then Final Project Presentation during last Lab
Final Project Grading Sheet

Select one of four levels of increasing hardware complexity.

Board alone	Board with Keypad	Board Keypad and ADC	Board Keypad and vga Monitor
Basys2 board alone   o------------------------------o Combination Lock, Dff Clapper, DeBouncer Message, Mux, Decoder Traffic, FSM (BTN1,0)	Basys2 board and 16-key keypad o------------------------------o Combination Lock, KP	Basys2 board and keypad with ADC o------------------------------o Analog Digital Converter, KP adc vga source files adc mouse image vga source files Rotate knob or insert between -9 and +9 Volts at protoboard pin 15 rel to pin 28 (gnd)	Basys2 board, keypad or keyboard and VGA monitor o------------------------------o Elevator, VGA, Katie Bills   Elevator, VGA, KB.bit Elevator 1, VGA   El1.bit Elevator 2, VGA   El2.bit TTT, VGA   TTT.bit Traffic, VGA (BTN1,0) .zip Traffic.bit   Traffic_goal.bit

• Xilinx Guides
  • Xilinx schematic tutorial
  • Xilinx verilog tutorial
  • Vivado 2016.1 User Guide
• Digilent Board
  • Basys2 Board Reference Manual (repeated)
  • Basys2 Board Schematics
  • JTAG Warning
• Digilent Agent
  • Digilent Adept System v2.8.1
  • Adept Suite User’s Manual
  • Adept Quick Start Guide

Enhancing Data Input and Output (PS/2, VGA) Instructions
Sample Monitor Display (VGA)   Keyboard scancodes
Module Organization Simplified   Detailed   Compiles with warnings   Top Module Simplified
Project source files (VGA)   Objective Hints

Getting started with Xilinx Vivado in list, screenshot, and video forms.

Follows these steps to create source files and then process those sources to program a Basys3 board.
01_New_Project 02_Edit_constr 03_Add_copy_of 04_Edit_source 05_Tools_Proje 06_Tools_Proje 07_Run_Implem 08_Select_Gene 09_Select_Open 10_Select_Open 11_Local_Serve 12_Program_dev   13_Flash_right 14_Flash_selec 15_Flash_progr 16_Flash_brows 17_Flash_Apply 18_Flash_succe 19_Flash_power   Intro to Videos vid start Vivado vid end Vivado vid alt Vivado

Your Lab grade comes from your Lab work you adequately document in your Lab Notebook as described in Grading_Policy.
ECE3700 Labs at University of Utah, Kalla   ECE3700 Labs at University of Utah, Brunvand   CS/EE3710 Labs at University of Utah
EE2700 Labs at Weber State University
XST User Guide (VHDL and Verilog examples)

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